1. Field of the Invention
The present invention relates to a synchronization circuit. It may be applied in the field of monitors, and more particularly in the field of television receivers.
A synchronization circuit may be used to set the rate at which an electron beam scans a screen. Synchronization signals in this context contain a timing information element used to set the start of a line and the start of a frame. A frame may contain all of the lines needed to form an image on the screen of a monitor.
Horizontal synchronization signals as well as vertical synchronization signals, also called line synchronization signals and frame synchronization signals respectively, are used for the production, by means of a phase-locked loop, of the scanning signals needed for the scanning of the screen by an electron beam.
The invention shall be described in the context of the processing of television signals without thereby in any way limiting the scope of the invention.
2. Discussion of the Related Art
In a television receiver, the synchronization signals are extracted from a video signal and given to a phase-locked loop. FIG. 1 shows a vertical synchronization signal VSYNCI and a horizontal synchronization signal HSYNCI, both extracted from a video signal. The vertical synchronization signal VSYNCI is a half-wave periodic rectangular-pulse signal with a high level 100, referred to as a frame flyback pulse, and a low level 101. During the frame flyback pulse 100 of the vertical synchronization signal VSYNCI, the working of the phase-locked loop, which is connected to the output of the synchronization circuits, is inhibited.
The horizontal synchronization signal HSYNCI is a sequence of line synchronization pulses 102 identically spaced out in time, each pulse corresponding to the synchronization of a line. This signal also has start-of-frame signal pulses 103 and end-of-frame signal pulses 104, respectively called post-equalization and pre-equalization pulses. The end-of-frame signal pulses 104 announce the frame flyback pulse. As for the start-of-frame signal pulses 103, they represent the display standard used.
The number of lines displayed on the screen differs according to the resolution used, as well as the display standards used in different regions of the world. Whereas current images have 525 lines or 625 lines, new standards specify 1024 lines. In addition, the frequency of refreshing the images on the screen, which may be about 25 images per second, also depends on the standard used.
The start-of-frame and end-of-frame signal pulses are positioned between line synchronization pulses. As a result, the frequency of the pulses of the horizontal synchronization signal at the start and at the end of a frame is twice as great as it is during the rest of the frame. The shape of the synchronization signals may then raise a problem.
The resulting changes of frequency due to the above signals interferes with the functioning of the phase-locked loop, which is connected to the synchronization signals after the synchronization circuit. The phase-locked loop may then go out of its range of operation.
The large number of standards and their varied nature dictate the use of systems that enable the processing of all types of synchronization signals. These systems should be capable of analyzing the synchronization signals whatever the display standard used, and of modifying them so as to improve the working of the phase-locked loops. Furthermore, these systems may include circuits designed to generate synchronization signals.
According to an embodiment of the invention, therefore, there is proposed a circuit capable of carrying out the following functions: receiving horizontal and vertical synchronization signals of any kind, measuring their period or acquiring information elements that represent the shape of these signals and producing a horizontal synchronization signal devoid of end-of-frame signal pulses 104 and a vertical synchronization signal whose frame flyback pulse 100 is extended during the start-of-frame signal pulses 103. This being achieved, the working of the phase-locked loop is suspended during the start-of-frame signalling pulses 103 and it no longer receives the end-of-frame signal pulses 104.
One aim of the invention is to create a synchronization circuit that may be integrated into all types of monitors.